In the field of semiconductor devices, the frequency of operation of the devices is constantly increasing. For clocked logic devices, therefore, signal evaluation time is decreasing. That is, the time allotted for a logic input to propagate to a logic output is decreasing. Domino circuits are used in integrated circuits to speed operating time. In a domino circuit, data is received on a first transition of a clock, and the signal is coupled to other circuitry on a next transition of the clock.
Conventional domino circuitry includes dynamic circuitry coupled to static gate circuits. The dynamic circuitry pre-charges an input of the static circuitry when a clock signal is low, and couples an input data signal to the static circuitry when the clock signal is high. The dynamic circuitry includes n-type metal oxide semiconductor (NMOS) pull-down circuitry. If the NMOS pull-down circuitry comprises low threshold voltage transistors, the domino circuitry is susceptible to noise.
The pull-down circuitry can comprise serially coupled pull down transistors. The speed of this serial pull-down circuitry can adversely impact the operation of the domino circuit by slowing the operation, or increasing noise susceptibility.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a domino circuit which has good operation speed characteristics. There is also a need for a domino circuit that has adequate noise immunity.